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INTEGRATED CIRCUITS
DATA SHEET
SAA7128H; SAA7129H Digital video encoder
Product specification Supersedes data of 2000 Mar 08 2002 Oct 15
Philips Semiconductors
Product specification
Digital video encoder
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 8 8.1 8.2 9 9.1 10 11 11.1 11.2 11.3 11.4 11.5 12 13 14 15 16 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Versatile fader Data manager Encoder RGB processor SECAM processor Output interface/DACs Synchronization Clock I2C-bus interface Input levels and formats Bit allocation map I2C-bus format Slave receiver Slave transmitter CHARACTERISTICS Explanation of RTCI data bits Teletext timing APPLICATION INFORMATION Analog output voltages PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods REVISION HISTORY DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
SAA7128H; SAA7129H
2002 Oct 15
2
Philips Semiconductors
Product specification
Digital video encoder
1 FEATURES
SAA7128H; SAA7129H
* Monolithic CMOS 3.3 V device, 5 V I2C-bus optional * Digital PAL/NTSC/SECAM encoder * System pixel frequency 13.5 MHz * 54 MHz double-speed multiplexed D1 interface capable of splitting data into two separate channels (encoded and baseband) * Three Digital-to-Analog Converters (DACs) for CVBS (CSYNC), VBS (CVBS) and C (CVBS) two times oversampled with 10-bit resolution (signals in brackets optional) * Three DACs for RED (CR), GREEN (Y) and BLUE (CB) two times oversampled with 9-bit resolution (signals in brackets optional) * Alternatively, an advanced composite sync is available on the CVBS output for RGB display centring * Real-time control of subcarrier * Cross-colour reduction filter * Closed captioning encoding and World Standard Teletext (WST) and North-American Broadcast Text System (NABTS) teletext encoding including sequencer and filter * Copy Generation Management System (CGMS) encoding (CGMS described by standard CPR-1204 of EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via I2C-bus * Fast I2C-bus control port (400 kHz) * Line 23 Wide Screen Signalling (WSS) encoding * Video Programming System (VPS) data encoding in line 16 (50/625 lines counting) * Encoder can be master or slave * Programmable horizontal and vertical input synchronization phase * Programmable horizontal sync output phase * Internal Colour Bar Generator (CBG) 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7128H SAA7129H QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm VERSION SOT307-2
(1) MacrovisionTM is a trademark of the Macrovision Corporation.
* MacrovisionTM(1) Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; this applies to SAA7128H only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information * Controlled rise/fall times of output syncs and blanking * On-chip crystal oscillator (3rd-harmonic or fundamental crystal) * Down mode (low output voltage) or power-save mode of DACs * QFP44 package. 2 GENERAL DESCRIPTION
The SAA7128H; SAA7129H encodes digital CB-Y-CR video data to an NTSC, PAL or SECAM CVBS or S-video signal. Simultaneously, RGB or bypassed but interpolated CB-Y-CR signals are available via three additional DACs. The circuit at a 54 MHz multiplexed digital D1 input port accepts two ITU-R BT.656 compatible CB-Y-CR data streams with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data with overlay and MPEG decoded data without overlay, whereas one data stream is latched at the rising, the other one at the falling clock edge. It includes a sync/clock generator and on-chip DACs.
2002 Oct 15
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Philips Semiconductors
Product specification
Digital video encoder
4 QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD Vi Vo(p-p) RL LElf(i) LElf(d) Tamb analog supply voltage digital supply voltage analog supply current digital supply current input signal voltage levels analog output signal voltages Y, C and CVBS without load (peak-to-peak value) load resistance low frequency integral linearity error low frequency differential linearity error ambient temperature PARAMETER
SAA7128H; SAA7129H
MIN. 3.15 3.0 - - 1.25 75 - - 0
TYP. 3.3 3.3 130 75 1.35 - - - -
MAX. 3.45 3.6 150 100 1.50 300 3 1 70
UNIT V V mA mA V LSB LSB C
TTL compatible
2002 Oct 15
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2002 Oct 15
RESET SDA 40 VDD(I2C) SA 20 21 I2C-BUS INTERFACE 42 SCL 41 35
5
Philips Semiconductors
Digital video encoder
BLOCK DIAGRAM
VDDA1 XTALI XTALO RCV1 RCV2 TTXRQ XCLK 34 7 8 43 37 LLC1 4
VDDA3 VDDA2 VDDA4 28 31 36
25
SAA7128H SAA7129H
clock and timing I2C-bus control
SYNC/CLOCK
I2C-bus control
I2C-bus control I2C-bus control
MP7 to MP0
9 to 16 MPpos SWITCH
MPA
MP FADER
Y ENCODER CB-CR
Y OUTPUT INTERFACE
30 D 27 A 24 22
CVBS (CSYNC) VBS (CVBS) C (CVBS) VSSA1 VSSA2 VSSA3 RED GREEN BLUE
MPneg
MPB
C
VP
5
I2C-bus control TTX 44 I2C-bus control Y D RGB PROCESSOR A 5 18 38 6 17 39 2 3 19
MHB572
I2C-bus control
32 33 23 26 29
CB-CR
SAA7128H; SAA7129H
VSSD1 VSSD2 VSSD3 VDDD1 VDDD2 VDDD3
SP
AP
RTCI
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Digital video encoder
6 PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 TYPE - I I I supply supply I/O I/O I I I I I I I I supply supply I digital supply voltage 2 digital ground 2 reserved pin; do not connect
SAA7128H; SAA7129H
SYMBOL RES SP AP LLC1 VSSD1 VDDD1 RCV1 RCV2 MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0 VDDD2 VSSD2 RTCI
DESCRIPTION test pin; connected to digital ground for normal operation test pin; connected to digital ground for normal operation line-locked clock input; this is the 27 MHz master clock digital ground 1 digital supply voltage 1 raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal raster control 2 for video port; this pin provides an HS pulse of programmable length or receives an HS pulse double-speed 54 MHz MPEG port; it is an input for "ITU-R BT.656" style multiplexed CB-Y-CR data; data is sampled on the rising and falling clock edge; data sampled on the rising edge is then sent to the encoding part of the device; data sampled on the falling edge is sent to the RGB part of the device (or vice versa, depending on programming)
real-time control input; if the LLC1 clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the respective decoder to improve the signal quality sense input for I2C-bus voltage; connect to I2C-bus supply select I2C-bus address; LOW selects slave address 88H, HIGH selects slave address 8CH analog ground 1 for RED (CR), C (CVBS) and GREEN (Y) outputs analog output of RED (CR) signal analog output of chrominance (CVBS) signal analog supply voltage 1 for RED (CR) and C (CVBS) outputs analog output of GREEN (Y) signal analog output of VBS (CVBS) signal analog supply voltage 2 for VBS (CVBS) and GREEN (Y) outputs analog output of BLUE (CB) signal analog output of CVBS (CSYNC) signal analog supply voltage 3 for BLUE (CB) and CVBS (CSYNC) outputs analog ground 2 for VBS (CVBS), BLUE (CB) and CVBS (CSYNC) outputs analog ground 3 for the DAC reference ladder and the oscillator crystal oscillator output crystal oscillator input; if the oscillator is not used, this pin should be connected to ground analog supply voltage 4 for the DAC reference ladder and the oscillator 6
VDD(I2C) SA VSSA1 RED C VDDA1 GREEN VBS VDDA2 BLUE CVBS VDDA3 VSSA2 VSSA3 XTALO XTALI VDDA4 2002 Oct 15
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
supply I supply O O supply O O supply O O supply supply supply O I supply
Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
SYMBOL XCLK VSSD3 VDDD3 RESET
PIN 37 38 39 40
TYPE O supply supply I digital ground 3 digital supply voltage 3
DESCRIPTION clock output of the crystal oscillator
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode; PAL black burst on CVBS, VBS and C; RGB outputs set to lowest voltage. The I2C-bus receiver waits for the START condition. I2C-bus serial clock input I2C-bus serial data input/output teletext request output, indicating when text bits are requested teletext bit stream input
SCL SDA TTXRQ TTX
41 42 43 44
I I/O O I
36 VDDA4
39 VDDD3
40 RESET
35 XTALI
37 XCLK
handbook, full pagewidth
34 XTALO
43 TTXRQ
38 VSSD3
42 SDA
41 SCL
44 TTX
RES 1 SP 2 AP 3 LLC1 4 VSSD1 5 VDDD1 6 RCV1 7 RCV2 8 MP7 9 MP6 10 MP5 11
33 VSSA3 32 VSSA2 31 VDDA3 30 CVBS 29 BLUE
SAA7128H SAA7129H
28 VDDA2 27 VBS 26 GREEN 25 VDDA1 24 C 23 RED
SA 21
VDDD2 17
VSSD2 18
VDD(I2C) 20
VSSA1 22
MP4 12
MP3 13
MP2 14
MP1 15
MP0 16
RTCI 19
MHB573
Fig.2 Pin configuration.
2002 Oct 15
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Philips Semiconductors
Product specification
Digital video encoder
7 FUNCTIONAL DESCRIPTION
SAA7128H; SAA7129H
Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using 50 Hz field rate. VPS data for program dependent automatic start and stop of such featured VCR's is loadable via I2C-bus. The IC also contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with Macrovision. It is also possible to load data for copy generation management system into line 20 of every field (525/60 line counting). A number of possibilities are provided for setting different video parameters, such as: * Black and blanking level control * Colour subcarrier frequency * Variable burst amplitude, etc. During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to input mode and the encoder is set to PAL mode and outputs a `black burst' signal on CVBS and S-video outputs, while RGB outputs are set to their lowest output voltages. A reset forces the I2C-bus interface to abort any running bus transfer. 7.1 Versatile fader
The digital video encoder encodes digital luminance and colour difference signals into analog CVBS, S-video and simultaneously RGB or CR-Y-CB signals. NTSC-M, PAL-B/G, SECAM and sub-standards are supported. Both interlaced and non-interlaced operation is possible for all standards. The basic encoder function consists of subcarrier generation and colour modulation and insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of "RS-170-A" and "ITU-R BT.470-3". For ease of analog post filtering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. The total filter transfer characteristics are illustrated in Figs 8 to 13. The DACs for Y, C and CVBS are realized with full 10-bit resolution; 9-bit resolution for RGB output. The CR-Y-CB to RGB dematrix can be bypassed optionally in order to provide the upsampled CR-Y-CB input signals. The 8-bit multiplexed CB-Y-CR formats are "ITU-R BT.656" (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in slave mode. Two independent data streams can be processed, one latched by the rising edge of LLC1, the other latched by the falling edge of LLC1. The purpose of that is e.g. to forward one of the data streams containing both video and On-Screen Display (OSD) information to the RGB outputs, and the other stream containing video only to the encoded outputs CVBS and S-video. For optimum display of RGB signals through a euro-connector TV set, optionally on the CVBS output an early composite sync pulse (up to 31 LLC1 clock periods) can be provided. As a further alternative, the VBS and C outputs may provide a second and third CVBS signal. It is also possible to connect a Philips digital video decoder (SAA7111, SAA7711A, SAA7112 or SAA7151B) to the SAA7128H; SAA7129H. Via the RTCI pin, connected to RTCO of a decoder, information concerning actual subcarrier, PAL-ID and (with SAA7111 and newer types) definite subcarrier phase can be inserted. The device synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock.
Important note: whenever the fader is activated with the SYMP bit set to a logic 1 (enabling the detection of embedded Start of Active Video (SAV) and End of Active Video (EAV)), codes 00H and FFH are not allowed within the actual video data (as prescribed by "ITU-R BT.656", anyway). If SAV (00H) has been detected, the fader automatically passes 100% of the respective signal until SAV will be detected. Within the digital video encoder, two data streams can be faded against each other; these data streams can be input to the double speed MPEG port, which is able to separate two independent 27 MHz data streams MPA and MPB via a cross switch controlled by EDGE1 and EDGE2.
handbook, halfpage
MPpos
EDGE1 = 0
MPA
G ED
E1
=1
ED
GE
MPneg
EDGE2 = 1
2=
0
MPB
MHB574
Fig.3 Cross switch.
2002 Oct 15
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Philips Semiconductors
Product specification
Digital video encoder
7.1.1 CONFIGURATION EXAMPLES
SAA7128H; SAA7129H
7.1.1.3 Configuration 3
Figs 4 to 7 show examples on how to configure the fader between the input ports and the outputs, separated into the composite (and S-video) encoder and the RGB encoder.
Input MPB is passed directly to the RGB output, assuming e.g. it contains video including overlay. MPA is equivalently passed through the inactive fader to the composite (and S-video) output, assuming e.g. it contains video excluding overlay (RGBIN = 0, ENCIN = 1).
7.1.1.1
Configuration 1
Input MPA can be faded into MPB. The resulting output of the fader is then encoded simultaneously to composite (and S-video) and RGB output (RGBIN = ENCIN = 1). In this example, either MPA or MPB could be an overlay (menu) signal to be faded smoothly in and out.
MPA
FADER BYPASS
ENCODER PATH
e.g. video recorder
MPB
RGB PATH
e.g. TV
FADER MPA MPB MP OUTPUT VP
ENCODER PATH
e.g. video recorder
MHB577
Fig.6 Configuration 3.
RGB PATH
e.g. TV
7.1.1.4
MHB575
Configuration 4
Only MPB input is in use; its signal appears both composite (and S-video) and RGB encoded (RGBIN = ENCIN = 0).
Fig.4 Configuration 1.
handbook, halfpage
7.1.1.2
Configuration 2
Input MPA can be faded into MPB. The resulting output of the fader is then encoded to RGB output, while the signal coming from MPB is fed directly to composite (and S-video) output (RGBIN = 1, ENCIN = 0). Also in this example, either MPA or MPB could be an overlay (menu) signal to be faded smoothly in and out, whereas the overlay appears only in the RGB output connected to the TV set.
MPA
ENCODER PATH
e.g. video recorder
MPB
RGB PATH
e.g. TV
MHB578
Fig.7 Configuration 4.
FADER MPA MPB MP OUTPUT VP
ENCODER PATH
e.g. video recorder
RGB PATH
e.g. TV
MHB576
Fig.5 Configuration 2.
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Philips Semiconductors
Product specification
Digital video encoder
7.1.2 PARAMETERS OF THE FADER 7.3 7.3.1 Encoder
SAA7128H; SAA7129H
Basically, there are three independent fade factors available, allowing for the equation: Output = ( FADEx x ln1 ) + [ ( 1 - FADEx ) x ln2 ] Where x = 1, 2 or 3 Factor FADE1 is effective, when a colour in the data stream fed to the MPEG port fader input is recognized as being between KEY1L and KEY1U. That means, the colour is not identified by a single numeric value, but an upper and lower threshold in a 24-bit YUV colour space can be defined. FADE1 = 00H results in 100% signal at the MPEG port fader input and 0% signal at the fader Video port input. Variation of 63 steps is possible up to FADE1 = 3FH, resulting in 0% signal at the MPEG port fader input and 100% signal at the fader Video port input. Factor FADE2 is effective, when a colour in the data stream fed to the MPEG port fader input is recognized as being between KEY2L and KEY2U. FADE2 is to be seen in conjunction with a colour that is defined by a 24-bit internal Colour Look-Up Table (CLUT). FADE2 = 00H results in 100% of the internally defined LUT colour and 0% signal at the fader Video port input. Variation of 63 steps is possible up to FADE2 = 3FH, resulting in 0% of the internally defined LUT colour and 100% signal at the fader Video port input. Finally, factor FADE3 is effective, when a colour in the data stream fed to the MPEG port fader input is recognized as neither being between KEY1L and KEY1U nor being between KEY2L and KEY2H. FADE3 = 00H results in 100% signal at the MPEG port fader input and 0% signal at the fader Video port input. Variation of 63 steps is possible up to FADE3 = 3FH, resulting in 0% signal at the MPEG port fader input and 100% signal at the fader Video port input. Optionally, all upper and lower thresholds can be ignored, enabling to fade signals only against the LUT colour. If bit CFADM is set HIGH, all data at the MPEG port fader are faded against the LUT colour, if bit CFADV is set HIGH, all data at the Video port fader are faded against the LUT colour. 7.2 Data manager
VIDEO PATH
The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y and C signals. Luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a fixed synchronization pulse tip level in accordance with standard composite synchronization schemes. Other manipulations used for the Macrovision anti-taping process such as additional insertion of AGC super-white pulses (programmable in height) are supported by the SAA7128H only. In order to enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, providing luminance in 10-bit resolution. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 10 and 11. Appropriate transients at start/end of active video and for synchronization pulses are ensured. Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y and C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 8 and 9. The amplitude, beginning and ending of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in a 10-bit resolution is provided on the subcarrier. The numeric ratio between Y and C outputs is in accordance with the respective standards.
In the data manager, alternatively to the external video data, a pre-defined colour look-up table located in this block can be read out in a pre-defined sequence (8 steps per active video line), achieving a colour bar test pattern generator without the need for an external data source.
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Philips Semiconductors
Product specification
Digital video encoder
7.3.2 TELETEXT INSERTION AND ENCODING 7.4
SAA7128H; SAA7129H
RGB processor
Pin TTX receives a WST or NABTS teletext bitstream sampled at the LLC clock. Two protocols are provided: * At each rising edge of output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at input pin TTX * The signal TTXRQ performs only a single LOW-to-HIGH transition and remains at HIGH level for 360, 296 or 288 teletext bits, depending on the chosen standard. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which are selectable independently for both fields. The internal insertion window for text is set to 360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Fig.23. 7.3.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING
This block contains a dematrix in order to produce red, green and blue signals to be fed to a SCART plug. Before Y, CB and CR signals are de-matrixed, individual gain adjustment for Y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. The transfer curves of luminance and colour difference components of RGB are illustrated in Figs 12 and 13. 7.5 SECAM processor
SECAM specific pre-processing is achieved by a pre-emphasis of colour difference signals (for gain and phase see Figs 14 and 15). A baseband frequency modulator with a reference frequency shifted from 4.286 MHz to DC carries out SECAM modulation in accordance with appropriate standard or optionally wide clipping limits. After the HF pre-emphasis, also applied on a DC reference carrier (anti-Cloche filter; see Figs 16 and 17), line-by-line sequential carriers with black reference of 4.25 MHz (Db) and 4.40625 MHz (Dr) are generated using specified values for FSC programming bytes. Alternating phase reset in accordance with SECAM standard is carried out automatically. During vertical blanking, the so-called "bottle pulses" are not provided. 7.6 Output interface/DACs
Five bytes of VPS information can be loaded via the I2C-bus and will be encoded in the appropriate format into line 16. 7.3.4 CLOSED CAPTION ENCODER
Using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number where data is to be encoded in, can be modified in a certain range. The data clock frequency is in accordance with the definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode closed caption data for 50 Hz field frequencies at 32 times horizontal line frequency. 7.3.5 ANTI-TAPING (SAA7128H ONLY)
In the output interface, encoded Y and C signals are converted from digital-to-analog in a 10-bit resolution. Y and C signals are also combined to a 10-bit CVBS signal. The CVBS output occurs with the same processing delay (equal to 82 LLC clock periods, measured from MP input to the analog outputs) as the Y, C and RGB outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of conversion ranges. Red, green and blue signals are also converted from digital-to-analog, each providing a 9-bit resolution. Outputs of the DACs can be set together via software control to minimum output voltage (approximately 0.2 V DC) for either purpose. Alternatively, the buffers can be switched into 3-state output condition; this allows for a `wired AND' configuration with other 3-state outputs and can also be used as a power-save mode.
For more information contact your nearest Philips Semiconductors sales office.
2002 Oct 15
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Philips Semiconductors
Product specification
Digital video encoder
7.7 Synchronization
SAA7128H; SAA7129H
In slave mode, the horizontal trigger phase can be programmed to any point in the line, the vertical phase from line 0 to line 15 counted from the first serration pulse in half line steps. Whenever synchronization information cannot be derived directly from the inputs, the SAA7128H; SAA7129H will calculate it from the internal horizontal, vertical and PAL phase. This gives good flexibility with respect to external synchronization, but the circuit does not suppress illegal settings. In such an event, the odd/even information may vanish as it does in the non-interlaced modes. In master mode, the line lengths are fixed to 1728 clocks at 50 Hz and 1716 clocks at 60 Hz. To allow non-interlaced frames, the field lengths can be varied by 0.5 lines. In the event of non-interlace, the SAA7128H; SAA7129H does not provide odd/even information and the output signal does not contain the PAL `Bruch sequence'. At the RCV1 pin the IC can provide: * A Vertical Sync (VS) signal with 2.5 (50 Hz) or 3 (60 Hz) lines duration * An odd/even signal which is LOW in odd fields * A Field Sequence (FSEQ) signal which is HIGH in the first field of the 4, 8 respectively 12 field sequences. At the RCV2 pin, there is a horizontal pulse of programmable phase and duration available. This pulse can be suppressed in the programmable inactive part of a field, giving a composite blank signal. The directions and polarities of the RCV ports can be chosen independently. Timing references can be found in Tables 52 and 60. 7.8 Clock
The synchronization of the SAA7128H; SAA7129H is able to operate in two modes; slave mode and master mode. In master mode (see Fig.19), the circuit generates all necessary timings in the video signal itself, and it can provide timing signals at the RCV1 and RCV2 ports. In slave mode, it accepts timing information either from the RCV pins or from the embedded timing data of the ITU-R BT.656 data stream. For the SAA7128H; SAA7129H, the only difference between master and slave mode is that it ignores the timing information at its inputs in master mode. Thus, if in slave mode, any timing information is missing, the IC will continue running free without a visible effect. But there must not be any additional pulses (with wrong phase) because the circuit will not ignore them. In slave mode (see Fig.18), an interface circuit decides, which signal is expected at the RCV1 port and which information is taken from its active slope. The polarity can be chosen. If PRCV1 is logic 0, the rising slope will be active. The signal can be: * A Vertical Sync (VS) pulse; the active slope sets the vertical phase * An odd/even signal; the active slope sets the vertical phase, the internal field flag to odd and optionally sets the horizontal phase * A Field Sequence (FSEQ) signal; it marks the first field of the 4 (NTSC), 8 (PAL) respectively 12 (SECAM) field sequences. In addition to the odd/even signal, it also sets the PAL phase and optionally defines the subcarrier phase. On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. The horizontal phase can be set via a separate input RCV2. In the event of VS pulses at RCV1, this is mandatory. It is also possible to set the signal path to blank via this input. From the ITU-R BT.656 data stream, the SAA7128H; SAA7129H decodes only the start of the first line in the odd field. All other information is ignored and may miss. If this kind of slave mode is active, the RCV pins may be switched to output mode.
The input to LLC1 can either be an external clock source or the buffered on-chip clock XCLK. The internal crystal oscillator can be run with either a 3rd-harmonic or a fundamental crystal frequency. 7.9 I2C-bus interface
The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write and readable, except one read only status byte. The I2C-bus slave address is defined as 88H with pin 21 (SA) tied LOW and as 8CH with pin 21 (SA) tied HIGH.
2002 Oct 15
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Philips Semiconductors
Product specification
Digital video encoder
7.10 Input levels and formats
SAA7128H; SAA7129H
The RGB, respectively CR-Y-CB path features a gain setting individually for luminance (GY) and colour difference signals (GCD). Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation.
The SAA7128H; SAA7129H expects digital Y, CB and CR data with levels (digital codes) in accordance with "ITU-R BT.601". For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. Table 1
"ITU-R BT.601" signal component levels
SIGNALS(1)
COLOUR Y White Yellow Cyan Green Magenta Red Blue Black Notes 1. Transformation: a) R = Y + 1.3707 x (CR - 128) b) G = Y - 0.3365 x (CB - 128) - 0.6982 x (CR - 128) c) B = Y + 1.7324 x (CB - 128). 235 210 170 145 106 81 41 16 CB 128 16 166 54 202 90 240 128 CR 128 146 16 34 222 240 110 128
R(2) 235 235 16 16 235 235 16 16
G(2) 235 235 235 235 16 16 16 16
B(2) 235 16 235 16 235 16 235 16
2. Representation of R, G and B (or CR, Y and CB) at the output is 9 bits at 27 MHz. Table 2 8-bit multiplexed format (similar to "ITU-R BT.601") BITS TIME 0 Sample Luminance pixel number Colour pixel number CB0 0 0 1 Y0 2 CR0 1 3 Y1 4 CB2 2 2 5 Y2 6 CR2 3 7 Y3
2002 Oct 15
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This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 7.11 Bit allocation map 2002 Oct 15 14 Philips Semiconductors
Digital video encoder
Table 3
Slave receiver (slave address 88H) DATA BYTE(1) SUBADDR D7 D6 VER1 0 WSS6 0 DECFIS 0 CG06 CG14 0 0 0 0 0 KEY1LU6 KEY1LV6 KEY1LY6 KEY2LU6 KEY2LV6 KEY2LY6 KEY1UU6 KEY1UV6 KEY1UY6 KEY2UU6 KEY2UV6 KEY2UY6 0 CFADEV 0 WSS5 WSS13 BS5 BE5 CG05 CG13 0 0 0 0 0 KEY1LU5 KEY1LV5 KEY1LY5 KEY2LU5 KEY2LV5 KEY2LY5 KEY1UU5 KEY1UV5 KEY1UY5 KEY2UU5 KEY2UV5 KEY2UY5 FADE15 FADE25 D5 VER0 0 WSS4 WSS12 BS4 BE4 CG04 CG12 0 YTRI 0 GY4 GCD4 SYMP KEY1LU4 KEY1LV4 KEY1LY4 KEY2LU4 KEY2LV4 KEY2LY4 KEY1UU4 KEY1UV4 KEY1UY4 KEY2UU4 KEY2UV4 KEY2UY4 FADE14 FADE24 D4 CCRDO 0 WSS3 WSS11 BS3 BE3 CG03 CG11 CG19 CTRI 0 GY3 GCD3 DEMOFF KEY1LU3 KEY1LV3 KEY1LY3 KEY2LU3 KEY2LV3 KEY2LY3 KEY1UU3 KEY1UV3 KEY1UY3 KEY2UU3 KEY2UV3 KEY2UY3 FADE13 FADE23 D3 CCRDE 0 0 WSS2 WSS10 BS2 BE2 CG02 CG10 CG18 RTRI 0 GY2 GCD2 CSYNC KEY1LU2 KEY1LV2 KEY1LY2 KEY2LU2 KEY2LV2 KEY2LY2 KEY1UU2 KEY1UV2 KEY1UY2 KEY2UU2 KEY2UV2 KEY2UY2 FADE12 FADE22 D2 0 WSS1 WSS9 BS1 BE1 CG01 CG09 CG17 GTRI 0 GY1 GCD1 MP2C KEY1LU1 KEY1LV1 KEY1LY1 KEY2LU1 KEY2LV1 KEY2LY1 KEY1UU1 KEY1UV1 KEY1UY1 KEY2UU1 KEY2UV1 KEY2UY1 FADE11 FADE21 D1 FSEQ 0 WSS0 WSS8 BS0 BE0 CG00 CG08 CG16 BTRI 0 GY0 GCD0 VP2C KEY1LU0 KEY1LV0 KEY1LY0 KEY2LU0 KEY2LV0 KEY2LY0 KEY1UU0 KEY1UV0 KEY1UY0 KEY2UU0 KEY2UV0 KEY2UY0 FADE10 FADE20 D0 O_E 00H 01H to 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH to 37H 38H 39H 3AH 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH VER2 0 WSS7 WSSON DECCOL 0 CG07 CG15 CGEN 0 0 0 CBENB KEY1LU7 KEY1LV7 KEY1LY7 KEY2LU7 KEY2LV7 KEY2LY7 KEY1UU7 KEY1UV7 KEY1UY7 KEY2UU7 KEY2UV7 KEY2UY7 0 CFADEM
REGISTER FUNCTION Status byte (read only) Null Wide screen signal Wide screen signal Real-time control, burst start Burst end Copy generation 0 Copy generation 1 CG enable, copy generation 2 Output port control Null Gain luminance for RGB Gain colour difference for RGB Input port control 1 Key colour 1 lower limit U Key colour 1 lower limit V Key colour 1 lower limit Y Key colour 2 lower limit U Key colour 2 lower limit V Key colour 2 lower limit Y Key colour 1 upper limit U Key colour 1 upper limit V Key colour 1 upper limit Y Key colour 2 upper limit U Key colour 2 upper limit V Key colour 2 upper limit Y Fade factor key colour 1 CFade, Fade factor key colour 2
CVBSEN1 CVBSEN0 CVBSTRI
SAA7128H; SAA7129H
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Oct 15 15 Philips Semiconductors DATA BYTE(1) REGISTER FUNCTION Fade factor other Look-up table key colour 2 U Look-up table key colour 2 V Look-up table key colour 2 Y VPS enable, input control 2 VPS byte 5 VPS byte 11 VPS byte 12 VPS byte 13 VPS byte 14 Chrominance phase Gain U Gain V Gain U MSB, real-time control, black level Gain V MSB, real-time control, blanking level CCR, blanking level VBI Null Standard control RTC enable, burst amplitude Subcarrier 0 Subcarrier 1 Subcarrier 2 Subcarrier 3 Line 21 odd 0 Line 21 odd 1 Line 21 even 0 Line 21 even 1 RCV port control Trigger control SUBADDR D7 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 0 LUTU7 LUTV7 LUTY7 VPSEN VPS57 VPS117 VPS127 VPS137 VPS147 CHPS7 GAINU7 GAINV7 GAINU8 GAINV8 CCRS1 0 DOWNB RTCE FSC07 FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17 SRCV11 HTRIG7 0 LUTU6 LUTV6 LUTY6 0 VPS56 VPS116 VPS126 VPS136 VPS146 CHPS6 GAINU6 GAINV6 DECOE DECPH CCRS0 0 DOWNA BSTA6 FSC06 FSC14 FSC22 FSC30 L21O06 L21O16 L21E06 L21E16 SRCV10 HTRIG6 D6 D5 FADE35 LUTU5 LUTV5 LUTY5 ENCIN VPS55 VPS115 VPS125 VPS135 VPS145 CHPS5 GAINU5 GAINV5 BLCKL5 BLNNL5 BLNVB5 0 INPI BSTA5 FSC05 FSC13 FSC21 FSC29 L21O05 L21O15 L21E05 L21E15 TRCV2 HTRIG5 D4 FADE34 LUTU4 LUTV4 LUTY4 RGBIN VPS54 VPS114 VPS124 VPS134 VPS144 CHPS4 GAINU4 GAINV4 BLCKL4 BLNNL4 BLNVB4 0 YGS BSTA4 FSC04 FSC12 FSC20 FSC28 L21O04 L21O14 L21E04 L21E14 ORCV1 HTRIG4 D3 FADE33 LUTU3 LUTV3 LUTY3 DELIN VPS53 VPS113 VPS123 VPS133 VPS143 CHPS3 GAINU3 GAINV3 BLCKL3 BLNNL3 BLNVB3 0 SECAM BSTA3 FSC03 FSC11 FSC19 FSC27 L21O03 L21O13 L21E03 L21E13 PRCV1 HTRIG3 D2 FADE32 LUTU2 LUTV2 LUTY2 VPSEL VPS52 VPS112 VPS122 VPS132 VPS142 CHPS2 GAINU2 GAINV2 BLCKL2 BLNNL2 BLNVB2 0 SCBW BSTA2 FSC02 FSC10 FSC18 FSC26 L21O02 L21O12 L21E02 L21E12 CBLF HTRIG2 D1 FADE31 LUTU1 LUTV1 LUTY1 EDGE2 VPS51 VPS111 VPS121 VPS131 VPS141 CHPS1 GAINU1 GAINV1 BLCKL1 BLNNL1 BLNVB1 0 PAL BSTA1 FSC01 FSC09 FSC17 FSC25 L21O01 L21O11 L21E01 L21E11 ORCV2 HTRIG1 D0 FADE30 LUTU0 LUTV0 LUTY0 EDGE1 VPS50 VPS110 VPS120 VPS130 VPS140 CHPS0 GAINU0 GAINV0 BLCKL0 BLNNL0 BLNVB0 0 FISE BSTA0 FSC00 FSC08 FSC16 FSC24 L21O00 L21O10 L21E00 L21E10 PRCV2 HTRIG0
Digital video encoder SAA7128H; SAA7129H
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Oct 15 16 Philips Semiconductors DATA BYTE(1) REGISTER FUNCTION Trigger control Multi control Closed caption, teletext enable RCV2 output start RCV2 output end MSBs RCV2 output TTX request H start TTX request H delay CSYNC advance, Vsync shift TTX odd request vertical start TTX odd request vertical end TTX even request vertical start TTX even request vertical end First active line Last active line TTX mode, MSB vertical Null Disable TTX line Disable TTX line Note SUBADDR D7 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH HTRIG10 SBLBN CCEN1 RCV2S7 RCV2E7 0 TTXHS7 TTXHD7 TTXOVS7 TTXOVE7 TTXEVS7 TTXEVE7 FAL7 LAL7 TTX60 0 LINE12 LINE20 D6 HTRIG9 BLCKON CCEN0 RCV2S6 RCV2E6 RCV2E10 TTXHS6 TTXHD6 TTXOVS6 TTXOVE6 TTXEVS6 TTXEVE6 FAL6 LAL6 LAL8 0 LINE11 LINE19 D5 HTRIG8 PHRES1 TTXEN RCV2S5 RCV2E5 RCV2E9 TTXHS5 TTXHD5 TTXOVS5 TTXOVE5 TTXEVS5 TTXEVE5 FAL5 LAL5 TTXO 0 LINE10 LINE18 D4 VTRIG4 PHRES0 SCCLN4 RCV2S4 RCV2E4 RCV2E8 TTXHS4 TTXHD4 TTXOVS4 TTXOVE4 TTXEVS4 TTXEVE4 FAL4 LAL4 FAL8 0 LINE9 LINE17 D3 VTRIG3 LDEL1 SCCLN3 RCV2S3 RCV2E3 0 TTXHS3 TTXHD3 TTXOVS3 TTXOVE3 TTXEVS3 TTXEVE3 FAL3 LAL3 TTXEVE8 0 LINE8 LINE16 D2 VTRIG2 LDEL0 SCCLN2 RCV2S2 RCV2E2 RCV2S10 TTXHS2 TTXHD2 TTXOVS2 TTXOVE2 TTXEVS2 TTXEVE2 FAL2 LAL2 TTXOVE8 0 LINE7 LINE15 D1 VTRIG1 FLC1 SCCLN1 RCV2S1 RCV2E1 RCV2S9 TTXHS1 TTXHD1 VS_S1 TTXOVS1 TTXOVE1 TTXEVS1 TTXEVE1 FAL1 LAL1 TTXEVS8 0 LINE6 LINE14 D0 VTRIG0 FLC0 SCCLN0 RCV2S0 RCV2E0 RCV2S8 TTXHS0 TTXHD0 VS_S0 TTXOVS0 TTXOVE0 TTXEVS0 TTXEVE0 FAL0 LAL0 TTXOVS8 0 LINE5 LINE13
Digital video encoder
CSYNCA4 CSYNCA3 CSYNCA2 CSYNCA1 CSYNCA0 VS_S2
SAA7128H; SAA7129H
1. All bits labelled `0' are reserved. They must be programmed with logic 0.
Product specification
Philips Semiconductors
Product specification
Digital video encoder
7.12 I2C-bus format I2C-bus address; see Table 5 SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK
SAA7128H; SAA7129H
Table 4 S Table 5
--------
DATA n
ACK
P
Explanation of Table 4 PART DESCRIPTION START condition 1000 100X or 1000 110X; note 1 acknowledge, generated by the slave subaddress byte data byte continued data bytes and ACKs STOP condition
S SLAVE ADDRESS ACK SUBADDRESS; note 2 DATA -------P Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. 7.13 Slave receiver Subaddress 26H SYMBOL WSS7 WSS6 WSS5 WSS4 WSS3 WSS2 WSS1 WSS0 Subaddress 27H SYMBOL WSSON - WSS13 WSS12 WSS11 WSS10 WSS9 WSS8 Wide screen signalling bits: subtitles field. DESCRIPTION 0 = wide screen signalling output is disabled; default state after reset 1 = wide screen signalling output is enabled This bit is reserved and must be set to logic 0. Wide screen signalling bits: reserved field. Wide screen signalling bits: aspect ratio field. DESCRIPTION Wide screen signalling bits: enhanced services field.
Table 6 BIT 7 6 5 4 3 2 1 0 Table 7 BIT 7 6 5 4 3 2 1 0
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Product specification
Digital video encoder
Table 8 BIT 7 Subaddress 28H SYMBOL DECCOL
SAA7128H; SAA7129H
DESCRIPTION 0 = disable colour detection bit of RTCI input 1 = enable colour detection bit of RTCI input; bit RTCE must be set to logic 1 (see Fig.22) 0 = field sequence as FISE in subaddress 61 1 = field sequence as FISE bit in RTCI input; bit RTCE must be set to logic 1 (see Fig.22) starting point of burst in clock cycles PAL: BS[5:0] = 33 (21H); default value after reset NTSC: BS[5:0] = 25 (19H)
6
DECFIS
5 4 3 2 1 0 Table 9 BIT 7 6 5 4 3 2 1 0
BS5 BS4 BS3 BS2 BS1 BS0 Subaddress 29H SYMBOL - - BE5 BE4 BE3 BE2 BE1 BE0
DESCRIPTION These 2 bits are reserved; each must be set to logic 0. ending point of burst in clock cycles PAL: BE[5:0] = 29 (1DH); default value after reset NTSC: BE[5:0] = 29 (1DH)
Table 10 Subaddress 2AH BIT 7 to 0 SYMBOL CG[07:00] DESCRIPTION LSB of the byte is encoded immediately after run-in, the MSB of the byte has to carry the CRCC bit, in accordance with the definition of copy generation management system encoding format.
Table 11 Subaddress 2BH BIT 7 to 0 SYMBOL CG[15:08] DESCRIPTION Second byte; the MSB of the byte has to carry the CRCC bit, in accordance with the definition of copy generation management system encoding format.
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Product specification
Digital video encoder
Table 12 Subaddress 2CH BIT 7 6 5 4 3 2 1 0 SYMBOL CGEN - - - CG19 CG18 CG17 CG16 Remaining bits of copy generation code.
SAA7128H; SAA7129H
DESCRIPTION 0 = copy generation data output is disabled; default state after reset 1 = copy generation data output is enabled These 3 bits are reserved; each must be set to logic 0.
Table 13 Subaddress 2DH BIT 7 6 5 4 3 2 1 0 SYMBOL CVBSEN1 CVBSEN0 CVBSTRI YTRI CTRI RTRI GTRI BTRI DESCRIPTION 0 = luminance output signal is switched to Y DAC; default state after reset 1 = CVBS output signal is switched to Y DAC 0 = chrominance output signal is switched to C DAC; default state after reset 1 = CVBS output signal is switched to C DAC 0 = DAC for CVBS output in 3-state mode (high-impedance) 1 = DAC for CVBS output in normal operation mode; default state after reset 0 = DAC for Y output in 3-state mode (high-impedance) 1 = DAC for Y output in normal operation mode; default state after reset 0 = DAC for C output in 3-state mode (high-impedance) 1 = DAC for C output in normal operation mode; default state after reset 0 = DAC for RED output in 3-state mode (high-impedance) 1 = DAC for RED output in normal operation mode; default state after reset 0 = DAC for GREEN output in 3-state mode (high-impedance) 1 = DAC for GREEN output in normal operation mode; default state after reset 0 = DAC for BLUE output in 3-state mode (high-impedance) 1 = DAC for BLUE output in normal operation mode; default state after reset
Table 14 Subaddress 38H BIT 7 to 5 4 to 0 SYMBOL - GY[4:0] DESCRIPTION These 3 bits are reserved; each must be set to logic 0. Gain luminance of RGB (CR, Y and CB) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = -6 (11010b), depending on external application.
Table 15 Subaddress 39H BIT 7 to 5 4 to 0 SYMBOL - GCD[4:0] DESCRIPTION These 3 bits are reserved; each must be set to logic 0. Gain colour difference of RGB (CR, Y and CB) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = -6 (11010b), depending on external application.
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Product specification
Digital video encoder
Table 16 Subaddress 3AH BIT 7 6 5 4 SYMBOL CBENB - - SYMP
SAA7128H; SAA7129H
DESCRIPTION 0 = data from input ports is encoded; default state after reset 1 = colour bar with fixed colours is encoded These 2 bits are reserved; each must be set to a logic 0. 0 = horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default state after reset 1 = horizontal and vertical trigger is decoded out of "ITU-R BT.656" compatible data at MPEG port 0 = YCBCR-to-RGB dematrix is active; default state after reset 1 = YCBCR-to-RGB dematrix is bypassed 0 = CVBS output signal is switched to CVBS DAC; default state after reset 1 = advanced composite sync is switched to CVBS DAC 0 = input data is twos complement from MPEG port fader input 1 = input data is straight binary from MPEG port fader input; default state after reset 0 = input data is twos complement from Video port fader input 1 = input data is straight binary from Video port fader input; default state after reset
3 2 1 0
DEMOFF CSYNC MP2C VP2C
Table 17 Subaddresses 42H to 44H and 48H to 4AH ADDRESS 42H 48H 43H 49H 44H 4AH BYTE KEY1LU KEY1UU KEY1LV KEY1UV KEY1LY KEY1UY DESCRIPTION Key colour 1 lower and upper limits for U, V and Y. If MPEG input signal is within the limits of key colour 1 the incoming signals at the Video port and MPEG port are added together according to the equation: FADE1 x video signal + (1 - FADE1) x MPEG signal Default value of all bytes after reset = 80H.
Table 18 Subaddresses 45H to 47H and 4BH to 4DH ADDRESS 45H 4BH 46H 4CH 47H 4DH BYTE KEY2LU KEY2UU KEY2LV KEY2UV KEY2LY KEY2UY DESCRIPTION Key colour 2 lower and upper limits for U,V and Y. If MPEG input signal is within the limits of key colour 2 the incoming signals at the Video port and MPEG port are added together according to the equation: FADE2 x video signal + (1 - FADE2) x LUT values Default value of all bytes after reset = 80H.
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Product specification
Digital video encoder
Table 19 Subaddress 4EH BIT 7 to 6 5 to 0 SYMBOL - FADE1[5:0]
SAA7128H; SAA7129H
DESCRIPTION These 2 bits are reserved; each must be set to logic 0. These 6 bits form factor FADE1 which determines the ratio between the MPEG and video input signal in the resulting video data stream if the key colour 1 is detected in the MPEG input signal. FADE1 = 00H: 100% MPEG, 0% video FADE1 = 3FH: 100% video, 0% MPEG; this is the default value after reset
Table 20 Subaddress 4FH BIT 7 SYMBOL CFADEM DESCRIPTION 0 = fader operates in normal mode; default state after reset 1 = the entire video input stream is faded with the colour stored in the LUT (subaddresses 51H to 53H) regardless of the MPEG input signal. The colour keys are disabled. 0 = fader operates in normal mode; default state after reset 1 = the entire MPEG input stream is faded with the colour stored in the LUT (subaddresses 51H to 53H) regardless of the video input signal. The colour keys are disabled. These 6 bits form factor FADE2 which determines the ratio between the LUT colour values (subaddresses 51H to 53H) and the video input signal in the resulting video data stream if the key colour 2 is detected in the MPEG input signal. FADE2 = 00H: 100% LUT colour, 0% video FADE2 = 3FH: 100% video, 0% LUT colour; this is the default value after reset Table 21 Subaddress 50H BIT 7 to 6 5 to 0 SYMBOL - FADE3[5:0] DESCRIPTION These 2 bits are reserved; each must be a logic 0. These 6 bits form factor FADE3 which determines the ratio between the MPEG and video input signal in the resulting video data stream if neither the key colour 1 nor the key colour 2 is detected in the MPEG input signal. FADE3 = 00H: 100% MPEG, 0% video FADE3 = 3FH: 100% video, 0% MPEG; this is the default value after reset
6
CFADEV
5 to 0
FADE2[5:0]
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Product specification
Digital video encoder
Table 22 Subaddress 51H BIT 7 to 0 SYMBOL LUTU[7:0]
SAA7128H; SAA7129H
DESCRIPTION LUT for the colour values inserted in case of key colour 2 U detection in the MPEG input data stream. LUTU[7:0] = 80H; default value after reset
Table 23 Subaddress 52H BIT 7 to 0 SYMBOL LUTV[7:0] DESCRIPTION LUT for the colour values inserted in case of key colour 2 V detection in the MPEG input data stream. LUTV[7:0] = 80H; default value after reset Table 24 Subaddress 53H BIT 7 to 0 SYMBOL LUTY[7:0] DESCRIPTION LUT for the colour values inserted in case of key colour 2 Y detection in the MPEG input data stream. LUTY[7:0] = 80H; default value after reset Table 25 Subaddress 54H BIT 7 6 5 4 3 2 1 0 SYMBOL VPSEN - ENCIN RGBIN DELIN VPSEL EDGE2 EDGE1 DESCRIPTION 0 = video programming system data insertion is disabled; default state after reset 1 = video programming system data insertion in line 16 is enabled This bit is not used and should be set to logic 0. 0 = encoder path is fed with MPB input data; fader is bypassed; default state after reset 1 = encoder path is fed with output signal of fader; see Section 7.1 0 = RGB path is fed with MPB input data; fader is bypassed; default state after reset 1 = RGB path is fed with output signal of fader; see Section 7.1 0 = not supported in current version; do not use 1 = recommended value; default state after reset 0 = not supported in current version; do not use 1 = recommended value; default state after reset 0 = MPB data is sampled on the rising clock edge; default state after reset 1 = MPB data is sampled on the falling clock edge 0 = MPA data is sampled on the rising clock edge; default state after reset 1 = MPA data is sampled on the falling clock edge
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Philips Semiconductors
Product specification
Digital video encoder
Table 26 Subaddress 55H BIT 7 to 0 SYMBOL VPS5[7:0]
SAA7128H; SAA7129H
DESCRIPTION Fifth byte of video programming system data in line 16; LSB first.
Table 27 Subaddress 56H BIT 7 to 0 SYMBOL VPS11[7:0] DESCRIPTION Eleventh byte of video programming system data in line 16; LSB first.
Table 28 Subaddress 57H BIT 7 to 0 SYMBOL VPS12[7:0] DESCRIPTION Twelfth byte of video programming system data in line 16; LSB first.
Table 29 Subaddress 58H BIT 7 to 0 SYMBOL VPS13[7:0] DESCRIPTION Thirteenth byte of video programming system data in line 16; LSB first.
Table 30 Subaddress 59H BIT 7 to 0 SYMBOL VPS14[7:0] DESCRIPTION Fourteenth byte of video programming system data in line 16; LSB first.
Table 31 Subaddress 5AH BIT 7 to 0 SYMBOL CHPS[7:0] DESCRIPTION Phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees. 0FH = PAL-B/G and data from input ports 3AH = PAL-B/G and data from look-up table 35H = NTSC-M and data from input ports 57H = NTSC-M and data from look-up table
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Philips Semiconductors
Product specification
Digital video encoder
Table 32 Subaddress 5BH BIT 7 to 0 SYMBOL GAINU[7:0]
SAA7128H; SAA7129H
DESCRIPTION These are the 8 LSBs of the 9-bit code that selects the variable gain for the CB signal; input representation in accordance with "ITU-R BT.601"; see Table 33. The MSB is held in subaddress 5DH; see Table 36.
Table 33 GAINU values CONDITIONS(1) white-to-black = 92.5 IRE GAINU[8:0] = 0 GAINU[8:0] = 118 (76H) white-to-black = 100 IRE GAINU[8:0] = 0 GAINU[8:0] = 125 (7DH) GAINU[8:0] = 106 (6AH) Note 1. All IRE values are rounded up Table 34 Subaddress 5CH BIT 7 to 0 SYMBOL GAINV[7:0] DESCRIPTION These are the 8 LSBs of the 9-bit code that selects the variable gain for the CR signal; input representation in accordance with "ITU-R BT.601"; see Table 35. The MSB is held in subaddress 5EH; see Table 38. ENCODING GAINU = -2.17 x nominal to +2.16 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal GAINU = -2.05 x nominal to +2.04 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal nominal GAINU for SECAM encoding
Table 35 GAINV values CONDITIONS(1) white-to-black = 92.5 IRE GAINV[8:0] = 0 GAINV[8:0] = 165 (A5H) white-to-black = 100 IRE GAINV[8:0] = 0 GAINV[8:0] = 175 (AFH) GAINV[8:0] = 129 (81H) Note 1. All IRE values are rounded up. ENCODING GAINV = -1.55 x nominal to +1.55 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal GAINV = -1.46 x nominal to +1.46 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal nominal GAINV for SECAM encoding
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Philips Semiconductors
Product specification
Digital video encoder
Table 36 Subaddress 5DH BIT 7 6 SYMBOL GAINU8 DECOE real-time control:
SAA7128H; SAA7129H
DESCRIPTION MSB of the 9-bit code that sets the variable gain for the CB signal; see Table 32. 0 = disable odd/even field control bit from RTCI 1 = enable odd/even field control bit from RTCI (see Fig.22)
5 to 0
BLCKL[5:0]
variable black level; input representation in accordance with "ITU-R BT.601"; see Table 37
Table 37 BLCKL values CONDITIONS(1) BLCKL = 0; note 2 BLCKL = 63 (3FH); note 2 BLCKL = 0; note 3 BLCKL = 63 (3FH); note 3 Notes 1. All IRE values are rounded up. 2. Output black level/IRE = BLCKL x 2/6.29 + 28.9. 3. Output black level/IRE = BLCKL x 2/6.18 + 26.5. Table 38 Subaddress 5EH BIT 7 6 SYMBOL GAINV8 DECPH real-time control: 0 = disable subcarrier phase reset bit from RTCI 1 = enable subcarrier phase reset bit from RTCI (see Fig.22) 5 to 0 BLNNL[5:0] variable blanking level; see Table 39 DESCRIPTION MSB of the 9-bit code that sets the variable gain for the CR signal; see Table 34. output black level = 29 IRE output black level = 49 IRE output black level = 27 IRE output black level = 47 IRE ENCODING(1)
white-to-sync = 140 IRE; note 2 recommended value: BLCKL = 58 (3AH)
white-to-sync = 143 IRE; note 3 recommended value: BLCKL = 51 (33H)
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Philips Semiconductors
Product specification
Digital video encoder
Table 39 BLNNL values CONDITIONS(1) BLNNL = 0; note 2 BLNNL = 63 (3FH); note 2 BLNNL = 0; note 3 BLNNL = 63 (3FH); note 3 Notes 1. All IRE values are rounded up. 2. Output black level/IRE = BLNNL x 2/6.29 + 25.4. 3. Output black level/IRE = BLNNL x 2/6.18 + 25.9; default after reset: 35H. Table 40 Subaddress 5FH BIT 7 6 5 4 3 2 1 0 SYMBOL CCRS1 CCRS0 BLNVB5 BLNVB4 BLNVB3 BLNVB2 BLNVB1 BLNVB0 output blanking level = 25 IRE output blanking level = 45 IRE output blanking level = 26 IRE output blanking level = 46 IRE
SAA7128H; SAA7129H
ENCODING(1)
white-to-sync = 140 IRE; note 2 recommended value: BLNNL = 46 (2EH)
white-to-sync = 143 IRE; note 3 recommended value: BLNNL = 53 (35H)
DESCRIPTION These 2 bits select the cross-colour reduction filter in luminance; see Table 41 and Fig.10. These 6 bits select the variable blanking level during vertical blanking interval is typically identical to value of BLNNL.
Table 41 Selection of cross-colour reduction filter CCRS1 0 0 1 1 CCRS0 0 1 0 1 no cross-colour reduction cross-colour reduction #1 active cross-colour reduction #2 active cross-colour reduction #3 active DESCRIPTION
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Philips Semiconductors
Product specification
Digital video encoder
Table 42 Subaddress 61H BIT 7 6 5 4 3 2 SYMBOL DOWNB DOWNA INPI YGS SECAM SCBW
SAA7128H; SAA7129H
DESCRIPTION 0 = DACs for R, G and B in normal operational mode 1 = DACs for R, G and B forced to lowest output voltage; default state after reset 0 = DACs for CVBS, Y and C in normal operational mode; default state after reset 1 = DACs for CVBS, Y and C forced to lowest output voltage 0 = PAL switch phase is nominal; default state after reset 1 = PAL switch phase is inverted compared to nominal if RTC is enabled; see Table 43 0 = luminance gain for white - black 100 IRE; default state after reset 1 = luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black 0 = no SECAM encoding; default state after reset 1 = SECAM encoding activated; bit PAL has to be set to logic 0 0 = enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 8 and 9) 1 = standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 8 and 9); default state after reset 0 = NTSC encoding (non-alternating V component) 1 = PAL encoding (alternating V component); default state after reset 0 = 864 total pixel clocks per line; default state after reset 1 = 858 total pixel clocks per line
1 0
PAL FISE
Table 43 Subaddress 62H BIT 7 SYMBOL RTCE DESCRIPTION 0 = no real-time control of generated subcarrier frequency; default state after reset 1 = real-time control of generated subcarrier frequency through SAA7151B or SAA7111; for timing see Fig.22 amplitude of colour burst; input representation in accordance with "ITU-R BT.601"; see Table 44
6 to 0
BSTA[6:0]
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Philips Semiconductors
Product specification
Digital video encoder
Table 44 BSTA values CONDITIONS(1)
SAA7128H; SAA7129H
ENCODING
white-to-black = 92.5 IRE; recommended value: BSTA = 63 (3FH) burst = 40 IRE; NTSC encoding BSTA = 0 to 2.02 x nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 2.82 x nominal white-to-black = 100 IRE; recommended value: BSTA = 67 (43H) burst = 43 IRE; NTSC encoding BSTA = 0 to 1.90 x nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 x nominal fixed burst amplitude with SECAM encoding Note 1. All IRE values are rounded up. Table 45 Subaddresses 63H to 66H ADDRESS 63H 64H 65H 66H Note 1. Examples: a) NTSC-M: fsc = 227.5, fllc = 1716 FSC = 569408543 (21F07C1FH). b) PAL-B/G: fsc = 283.7516, fllc = 1728 FSC = 705268427 (2A098ACBH). c) SECAM: fsc = 274.304, fllc = 1728 FSC = 681786290 (28A33BB2H). BYTE FSC[07:00] FSC[15:08] FSC[23:16] FSC[31:24] DESCRIPTION These 4 bytes are used to program the subcarrier frequency. FSC[31:24] is the most significant byte, FSC[07:00] is the least significant byte. fsc = subcarrier frequency (in multiples of line frequency) fllc = clock frequency (in multiples of line frequency) f sc 32 FSC = round ------ x 2 ; note 1 f llc recommended value: BSTA = 47 (2FH); default value after reset recommended value: BSTA = 45 (2DH)
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Philips Semiconductors
Product specification
Digital video encoder
Table 46 Subaddress 67H BIT 7 to 0 SYMBOL L21O[07:00]
SAA7128H; SAA7129H
DESCRIPTION First byte of captioning data, odd field. LSB of the byte is encoded immediately after run-in and framing code, the MSB of the byte has to carry the parity bit, in accordance with the definition of line 21 encoding format.
Table 47 Subaddress 68H BIT 7 to 0 SYMBOL L21O[17:10] DESCRIPTION Second byte of captioning data, odd field. The MSB of the byte has to carry the parity bit, in accordance with the definition of line 21 encoding format. Table 48 Subaddress 69H BIT 7 to 0 SYMBOL L21E[07:00] DESCRIPTION First byte of extended data, even field. LSB of the byte is encoded immediately after run-in and framing code, the MSB of the byte has to carry the parity bit, in accordance with the definition of line 21 encoding format. Table 49 Subaddress 6AH BIT 7 to 0 SYMBOL L21E[17:10] DESCRIPTION Second byte of extended data, even field. The MSB of the byte has to carry the parity bit, in accordance with the definition of line 21 encoding format.
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Philips Semiconductors
Product specification
Digital video encoder
Table 50 Subaddress 6BH BIT 7 6 5 SYMBOL SRCV11 SRCV10 TRCV2
SAA7128H; SAA7129H
DESCRIPTION These 2 bits define signal type on pin RCV1; see Table 51 0 = horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded frame sync of "ITU-R BT.656" input (at bit SYMP = HIGH); default state after reset 1 = horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW) 0 = pin RCV1 is switched to input; default state after reset 1 = pin RCV1 is switched to output 0 = polarity of RCV1 as output is active HIGH, rising edge is taken when input; default state after reset 1 = polarity of RCV1 as output is active LOW, falling edge is taken when input When CBLF = 0. If ORCV2 = 1, pin RCV2 provides an HREF signal (horizontal reference pulse that is defined by RCV2S and RCV2E, also during vertical blanking interval); default state after reset. If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1); default state after reset. When CBLF = 1. If ORCV2 = 1, pin RCV2 provides a `composite-blanking-not' signal, for example a reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking interval, which is defined by FAL and LAL. If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking signal.
4 3
ORCV1 PRCV1
2
CBLF
1 0
ORCV2 PRCV2
0 = pin RCV2 is switched to input; default state after reset 1 = pin RCV2 is switched to output 0 = polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively; default state after reset 1 = polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively
Table 51 Selection of the signal type on pin RCV1 SRCV11 0 0 1 1 SRCV10 0 1 0 1 RCV1 VS FS FSEQ - Frame Sync (odd/even) Field Sequence, vertical sync every fourth field (PAL = 0), eighth field (PAL = 1) or twelfth field (SECAM = 1) not applicable FUNCTION Vertical Sync each field; default state after reset
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Philips Semiconductors
Product specification
Digital video encoder
Table 52 Subaddress 6CH BIT 7 to 0 SYMBOL HTRIG[7:0]
SAA7128H; SAA7129H
DESCRIPTION These are the 8 LSBs of the 11-bit code that sets the horizontal trigger phase related to the signal on RCV1 or RCV2 input. The 3 MSBs are held in subaddress 6DH; see Table 53. Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Increasing HTRIG[10:0] decreases delays of all internally generated timing signals. Reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG[10:0] = 4FH (79).
Table 53 Subaddress 6DH BIT 7 6 5 4 3 2 1 0 SYMBOL HTRIG10 HTRIG9 HTRIG8 VTRIG4 VTRIG3 VTRIG2 VTRIG1 VTRIG0 Sets the vertical trigger phase related to signal on RCV1 input. Increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG[4:0] = 0 to 31 (1FH). DESCRIPTION These are the 3 MSBs of the horizontal trigger phase code; see Table 52.
Table 54 Subaddress 6EH BIT 7 SYMBOL SBLBN DESCRIPTION 0 = vertical blanking is defined by programming of FAL and LAL; default state after reset 1 = vertical blanking is forced in accordance with "ITU-R BT.624" (50 Hz) or RS170A (60 Hz) 0 = encoder in normal operation mode 1 = output signal is forced to blanking level; default state after reset These 2 bits select the phase reset mode of the colour subcarrier generator; see Table 55. These 2 bits select the delay on luminance path with reference to chrominance path; see Table 56. These 2 bits select field length control; see Table 57.
6 5 4 3 2 1 0
BLCKON PHRES1 PHRES0 LDEL1 LDEL0 FLC1 FLC0
Table 55 Selection of phase reset mode PHRES1 0 0 1 1 PHRES0 0 1 0 1 DESCRIPTION no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default value after reset reset every two lines or SECAM specific if bit SECAM = 1 reset every eight fields reset every four fields
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Philips Semiconductors
Product specification
Digital video encoder
Table 56 Selection of luminance path delay LDEL1 0 0 1 1 LDEL0 0 1 0 1 1 LLC luminance delay 2 LLC luminance delay 3 LLC luminance delay
SAA7128H; SAA7129H
LUMINANCE PATH DELAY no luminance delay; default value after reset
Table 57 Selection of field length control FLC1 0 0 1 1 FLC0 0 1 0 1 DESCRIPTION interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default value after reset non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 58 Subaddress 6FH BIT 7 6 5 4 3 2 1 0 SYMBOL CCEN1 CCEN0 TTXEN SCCLN4 SCCLN3 SCCLN2 SCCLN1 SCCLN0 0 = disables teletext insertion; default state after reset 1 = enables teletext insertion These 5 bits select the actual line where closed caption or extended data are encoded. line = (SCCLN[4:0] + 4) for M-systems line = (SCCLN[4:0] + 1) for other systems DESCRIPTION These 2 bits enable individual line 21 encoding; see Table 59.
Table 59 Selection of line 21 encoding CCEN1 0 0 1 1 CCEN0 0 1 0 1 LINE 21 ENCODING line 21 encoding off; default value after reset enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields
Table 60 Subaddress 70H BIT 7 to 0 SYMBOL RCV2S[7:0] DESCRIPTION These are the 8 LSBs of the 11-bit code that determines the start of the output signal on the RCV2 pin; the 3 MSBs of the 11-bit code are held at subaddress 72H; see Table 62. Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Leading sync slope at CVBS output coincides with leading slope of RCV2 out at RCV2S = 49H.
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Philips Semiconductors
Product specification
Digital video encoder
Table 61 Subaddress 71H BIT 7 to 0 SYMBOL RCV2E[7:0]
SAA7128H; SAA7129H
DESCRIPTION These are the 8 LSBs of the 11-bit code that determines the end of the output signal on the RCV2 pin; the 3 MSBs of the 11-bit code are held at subaddress 72H; see Table 62. Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Leading sync slope at CVBS output coincides with trailing slope of RCV2 out at RCV2E = 49H.
Table 62 Subaddress 72H BIT 7 6 5 4 3 2 1 0 SYMBOL - RCV2E10 RCV2E9 RCV2E8 - RCV2S10 RCV2S9 RCV2S8 This bit is reserved and must be set to a logic 0. These are the 3 MSBs of start of output signal code; see Table 60. DESCRIPTION This bit is reserved and must be set to a logic 0. These are the 3 MSBs of end of output signal code; see Table 61.
Table 63 Subaddress 73H BIT 7 to 0 SYMBOL TTXHS[7:0] PAL: TTXHS[7:0] = 42H NTSC: TTXHS[7:0] = 54H Table 64 Subaddress 74H BIT 7 to 0 SYMBOL TTXHD[7:0] DESCRIPTION Indicates the delay in clock cycles between rising edge of TTXRQ output and valid data at pin TTX. minimum value: TTXHD[7:0] = 2 Table 65 Subaddress 75H BIT 7 6 5 4 3 2 1 0 SYMBOL CSYNCA4 CSYNCA3 CSYNCA2 CSYNCA1 CSYNCA0 VS_S2 VS_S1 VS_S0 Vertical sync shift between RCV1 and RCV2 (switched to output); in master mode it is possible to shift Hsync (RCV2; CBLF = 0) against Vsync (RCV1; SRCV1 = 00). standard value: VS_S[2:0] = 3 DESCRIPTION Advanced composite sync against RGB output from 0 to 31 LLC clock periods. DESCRIPTION Start of signal on pin TTXRQ; see Fig.23.
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Philips Semiconductors
Product specification
Digital video encoder
Table 66 Subaddress 76H BIT 7 to 0 SYMBOL TTXOVS[7:0] DESCRIPTION
SAA7128H; SAA7129H
REMARKS PAL: TTXOVS = 05H; NTSC: TTXOVS = 06H
These are the 8 LSBs of the 9-bit code that determines the first line of occurrence of signal on pin TTXRQ in odd field. The MSB is held in subaddress 7CH; see Table 72. line = (TTXOVS[8:0] + 4) for M-systems line = (TTXOVS[8:0] + 1) for other systems
Table 67 Subaddress 77H BIT 7 to 0 SYMBOL TTXOVE[7:0] DESCRIPTION These are the 8 LSBs of the 9-bit code that determines the last line of occurrence of signal on pin TTXRQ in odd field. The MSB is held in subaddress 7CH; see Table 72. last line = (TTXOVE[8:0] + 3) for M-systems last line = TTXOVE[8:0] for other systems Table 68 Subaddress 78H BIT 7 to 0 SYMBOL TTXEVS[7:0] DESCRIPTION These are the 8 LSBs of the 9-bit code that determines the first line of occurrence of signal on pin TTXRQ in even field. The MSB is held in subaddress 7CH; see Table 72. first line = (TTXEVS[8:0] + 4) for M-systems first line = (TTXEVS[8:0] + 1) for other systems Table 69 Subaddress 79H BIT 7 to 0 SYMBOL TTXEVE[7:0] DESCRIPTION These are the 8 LSBs of the 9-bit code that determines the last line of occurrence of signal on pin TTXRQ in even field. The MSB is held in subaddress 7CH; see Table 72. last line = (TTXEVE[8:0] + 3) for M-systems last line = TTXEVE[8:0] for other systems Table 70 Subaddress 7AH BIT 7 to 0 SYMBOL FAL[7:0] DESCRIPTION These are the 8 LSBs of the 9-bit code that determines the first active line. The MSB is held in subaddress 7CH; see Table 72. FAL[8:0] = 0 coincides with the first field synchronization pulse. first active line = (FAL[8:0] + 4) for M-systems first active line = (FAL[8:0] + 1) for other systems REMARKS PAL: TTXEVE = 16H; NTSC: TTXEVE = 10H REMARKS PAL: TTXEVS = 04H; NTSC: TTXEVS = 05H REMARKS PAL: TTXOVE = 16H; NTSC: TTXOVE = 10H
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Philips Semiconductors
Product specification
Digital video encoder
Table 71 Subaddress 7BH BIT 7 to 0 SYMBOL LAL[7:0]
SAA7128H; SAA7129H
DESCRIPTION These are the 8 LSBs of the 9-bit code that determines the last active line. The MSB is held in subaddress 7CH; see Table 72. LAL[8:0] = 0 coincides with the first field synchronization pulse. last active line = (LAL[8:0] + 3) for M-systems last active line = LAL[8:0] for other systems
Table 72 Subaddress 7CH BIT 7 SYMBOL TTX60 DESCRIPTION 0 = enables NABTS (FISE = 1) or European teletext (FISE = 0); default state after reset 1 = enables World Standard Teletext 60 Hz (FISE = 1) MSB of the last active line code; see Table 71. 0 = new teletext protocol selected: at each rising edge of TTXRQ a single teletext bit is requested (see Fig.23); default state after reset 1 = old teletext protocol selected: the encoder provides a window of TTXRQ going HIGH; the length of the window depends on the chosen teletext standard (see Fig.23) MSB of the first active line code; see Table 70. MSB of the 9-bit code that selects the last line of occurrence of signal on pin TTXRQ in even field; see Table 69. MSB of the 9-bit code that selects the last line of occurrence of signal on pin TTXRQ in odd field; see Table 67. MSB of the 9-bit code that selects the first line of occurrence of signal on pin TTXRQ in even field; see Table 68. MSB of the 9-bit code that selects the first line of occurrence of signal on pin TTXRQ in odd field; see Table 66.
6 5
LAL8 TTXO
4 3 2 1 0
FAL8 TTXEVE8 TTXOVE8 TTXEVS8 TTXOVS8
Table 73 Subaddress 7EH BIT 7 to 0 SYMBOL LINE[12:5] DESCRIPTION Individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective LINE bits. Disabled line = LINEnn (50 Hz field rate). This bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE.
Table 74 Subaddress 7FH BIT 7 to 0 SYMBOL LINE[20:13] DESCRIPTION Individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective LINE bits. Disabled line = LINEnn (50 Hz field rate). This bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE.
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Philips Semiconductors
Product specification
Digital video encoder
7.14 Slave transmitter
SAA7128H; SAA7129H
The slave transmitter slave address is 89H. Table 75 Subaddress 00H BIT 7 6 5 4 SYMBOL VER2 VER1 VER0 CCRDO DESCRIPTION These 3 bits form the version identification number of the device: it will be changed with all versions of the IC that have different programming models; current version is 000 binary. 1 = closed caption bytes of the odd field have been encoded 0 = the bit is reset after information has been written to the subaddresses 67H and 68H; it is set immediately after the data has been encoded 1 = closed caption bytes of the even field have been encoded 0 = the bit is reset after information has been written to the subaddresses 69H and 6AH; it is set immediately after the data has been encoded not used; set to logic 0 1 = during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields, SECAM = 12 fields) 0 = not first field of a sequence 1 = during even field 0 = during odd field
3
CCRDE
2 1
- FSEQ
0
O_E
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Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
handbook, full pagewidth 6
MBE737
Gv
(dB)
0 -6
-12 -18 -24
(1) (2)
-30 -36 -42 -48 -54 0 (1) SCBW = 1. (2) SCBW = 0. 2 4 6 8 10 12 f (MHz) 14
Fig.8 Chrominance transfer characteristic 1.
handbook, halfpage
2
MBE735
Gv (dB) 0
(1)
(2)
-2
-4
-6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig.9 Chrominance transfer characteristic 2.
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Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
Gv handbook, full pagewidth (dB) 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
(4) (2) (3) (1)
6
MGD672
(1) (2) (3) (4)
CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0.
Fig.10 Luminance transfer characteristic 1.
handbook, halfpage
MBE736
1
Gv (dB) 0
(1)
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
(1) CCRS1 = 0; CCRS0 = 0.
Fig.11 Luminance transfer characteristic 2.
2002 Oct 15
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Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
handbook, full pagewidth
Gv 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54
MGB708
(dB)
0
2
4
6
8
10
12
f (MHz)
14
Fig.12 Luminance transfer characteristic in RGB.
handbook, full pagewidth
Gv 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54
MGB706
(dB)
0
2
4
6
8
10
12
f (MHz)
14
Fig.13 Colour difference transfer characteristic in RGB.
2002 Oct 15
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Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
handbook, full pagewidth
MGB705
10
Gv (dB) 8
6
4
2
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.14 Gain of SECAM pre-emphasis.
handbook,30 pagewidth full
MGB704
(deg)
20
10
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.15 Phase of SECAM pre-emphasis.
2002 Oct 15
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Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
handbook, full pagewidth
MGB703
20
Gv (dB) 16
12
8
4
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.16 Gain of SECAM anti-Cloche.
handbook, full pagewidth
MGB702
80
(deg) 60
40
20
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 f (MHz) 1.6
Fig.17 Phase of SECAM anti-Cloche.
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Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
handbook, full pagewidth
CVBS output
RCV2 input
79 LCC MP input 82 LCC
MHB579
HTRIG = 0 PRCV2 = 0. TRCV2 = 1. ORCV2 = 0.
Fig.18 Sync and video input timing.
handbook, full pagewidth
CVBS output
RCV2 output
MHB580
73 LCC
RCV2S = 0. PRCV2 = 0. ORCV2 = 1.
Fig.19 Sync and video output timing.
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Philips Semiconductors
Product specification
Digital video encoder
8 CHARACTERISTICS VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supply VDDA VDDD IDDA IDDD VIL VIH ILI Ci analog supply voltage digital supply voltage analog supply current digital supply current note 1 VDDD = 3.3 V; note 1 PARAMETER CONDITIONS
SAA7128H; SAA7129H
MIN.
MAX.
UNIT
3.15 3.0 - - -0.5 2.0 - clocks data I/Os at high-impedance - - -
3.45 3.6 150 100
V V mA mA
Inputs: LLC1, RCV1, RCV2, MP7 to MP0, RTCI, SA, RESET and TTX LOW-level input voltage HIGH-level input voltage input leakage current input capacitance +0.8 VDDD + 0.3 1 10 8 8 V V A pF pF pF
Outputs: RCV1, RCV2 and TTXRQ VOL VOH I2C-bus: VIL VIH Ii VOL Io TLLC1 tr tf tSU;DAT tHD;DAT LOW-level output voltage HIGH-level output voltage SDA and SCL LOW-level input voltage HIGH-level input voltage input current LOW-level output voltage (pin SDA) output current Vi = LOW or HIGH IOL = 3 mA during acknowledge -0.5 0.7VDD(I2C) -10 - 3 +0.3VDD(I2C) +10 0.4 - 41 60 60 5 6 - - V A V mA VDD(I2C) + 0.3 V IOL = 2 mA IOH = -2 mA - 2.4 0.4 - V V
Clock timing: LLC1 and XCLK cycle time duty factor tHIGH/TLLC1 duty factor tHIGH/TXCLK rise time fall time note 2 LLC1 input XCLK output typical 50% note 2 note 2 34 40 40 - - 6 3 ns % % ns ns
Input timing: RCV1, RCV2, MP7 to MP0, RTCI, SA and TTX input data set-up time input data hold time ns ns
2002 Oct 15
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Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
SYMBOL Crystal oscillator fn f/fn
PARAMETER
CONDITIONS -
MIN.
MAX.
UNIT
nominal frequency (usually 27 MHz) permissible deviation of nominal frequency
3rd harmonic note 3
30 +50 x 10-6
MHz
-50 x 10-6
CRYSTAL SPECIFICATION Tamb CL RS Cmot Cpar CL th td Vo(p-p) V Rint RL B LElf(i) LElf(d) td(pipe)(MP) Notes 1. At maximum supply voltage with highly active input signals. 2. The data is for both input and output direction. 3. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 4. For full digital range, without load, VDDA = 3.3 V. The typical voltage swing is 1.35 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V. 5. Referring to peak-to-peak analog voltages resulting from identical peak-to-peak digital codes. ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical) 0 8 - 1.5 - 20% 3.5 - 20% 7.5 4 - 1.25 - 1 75 -3 dB 10 - - 27 MHz - 70 - 80 1.5 + 20% 3.5 + 20% C pF fF pF
Data and reference signal output timing output load capacitance output hold time output delay time 40 - 18 pF ns ns
Outputs: C, VBS, CVBS and RGB output signal voltage (peak-to-peak value) note 4 inequality of output signal voltages internal serial resistance output load resistance output signal bandwidth of DACs low frequency integral linearity error of DACs low frequency differential linearity error of DACs total pipeline delay from MP port note 5 1.50 2 3 300 - 3 1 82 V % MHz LSB LSB LLC
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Philips Semiconductors
Product specification
Digital video encoder
SAA7128H; SAA7129H
handbook, full pagewidth
TLLC1 t HIGH 2.6 V 1.5 V 0.6 V tf t SU; DAT t HD; DAT not valid t SU; DAT t HD; DAT not valid 2.0 V MPpos 0.8 V tr
LLC1
MP input data
MPpos
MPneg
td th 2.4 V output data valid not valid valid 0.6 V
MHB581
Fig.20 Clock data timing.
handbook, full pagewidth
LLC
MP(n)
CB(0)
Y(0)
CR(0)
Y(1)
CB(2)
RCV2
MGB699
The data demultiplexing phase is coupled to the internal horizontal phase. The phase of the RCV2 signal is programmed to 262 for 50 Hz and to 234 for 60 Hz in this example in output mode (RCV2S).
Fig.21 Functional timing.
2002 Oct 15
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Philips Semiconductors
Product specification
Digital video encoder
8.1 Explanation of RTCI data bits
SAA7128H; SAA7129H
6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1), the SAA7128H; SAA7129H ignores its internally generated odd/even flag and takes the odd/even bit from RTCI input. 7. If the colour detection bit is enabled (RTCE = 1; DECCOL = 1) and no colour was detected (colour detection bit = 0), the subcarrier frequency is generated by the SAA7128H; SAA7129H. In the other case (colour detection bit = 1) the subcarrier frequency is evaluated out of FSCPLL increment. If the colour detection bit is disabled (RTCE = 1; DECCOL = 0), the subcarrier frequency is evaluated out of FSCPLL increment, independent of the colour detection bit of RTCI input.
1. The HPLL increment is not evaluated by the SAA7128H; SAA7129H. 2. The SAA7128H; SAA7129H generates the subcarrier frequency from the FSCPLL increment if enabled (see item 7.). 3. The PAL bit indicates the line with inverted (R - Y) component of colour difference signal. 4. If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of the subcarrier is reset in each line whenever the reset bit of RTCI input is set to logic 1. 5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the SAA7128H; SAA7129H takes this bit instead of the FISE bit in subaddress 61H.
HIGH-to-LOW transition handbook, full pagewidth count start LOW 128 RTCI
13
4 bits reserved HPLL increment (1)
0 22
3 bits reserved FSCPLL increment (2)
0 (4) (3)
(5) (6)
(7)
time slot: 0 1
14
19
64
67 69 68
72 74
not used in SAA7128H/29H
valid sample
invalid sample
8/LLC
MGL934
(8)
(1) (2) (3) (4) (5) (6) (7) (8)
SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment. SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit. Sequence bit: PAL: 0 = (R - Y) line normal, 1 = (R - Y) line inverted; NTSC: 0 = no change. Reset bit: only from SAA7111 and SAA7112 decoder. FISE bit: 0 = 50 Hz, 1 = 60 Hz. Odd/even bit: odd_even from external. Colour detection: 0 = no colour detected, 1 = colour detected. Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.
Fig.22 RTCI timing.
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Philips Semiconductors
Product specification
Digital video encoder
8.2 Teletext timing
SAA7128H; SAA7129H
Time ti(TTXW) is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s (WST) or 288 teletext bits at a text data rate of 5.7272 Mbits/s (NABTS). The insertion window is not opened if the control bit TTXEN is logic 0. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion.
Time tFD is the time needed to interpolate input data TTX and insert it into the CVBS and VBS output signal, such that it appears at tTTX = 9.78 s (PAL) or tTTX = 10.5 s (NTSC) after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ, a new teletext bit must be provided by the source (new protocol) or a window of TTXRQ going HIGH is provided and the number of teletext bits, depending on the chosen teletext standard, is requested at input pin TTX (old protocol). Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of outgoing horizontal synchronization pulse.
handbook, full pagewidth
CVBS/Y t TTX text bit #: TTX t PD TTXRQ (new) t FD 1 2 3 4 5 6 7 8 9 10 11 12 t i(TTXW) 13 14 15 16 17 18 19 20 21 22 23 24
TTXRQ (old)
MHB504
Fig.23 Teletext timing.
2002 Oct 15
47
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dbook, full pagewidth
2002 Oct 15 48
9
Philips Semiconductors
Digital video encoder
APPLICATION INFORMATION
DGND 10 H 1 nF 10 pF 27.0 MHz X1 3rd harmonic 35
+3.3 V digital 0.1 F 10 pF DGND use one capacitor for each VDDD XTAL 34 VDDD1 to VDDD3 6, 17, 39
+3.3 V analog 0.1 F AGND 0.1 F use one capacitor for each VDDA VDDA4 36 DAC1 VDDA1 to VDDA3 25, 28, 31 2 (1) 30 CVBS 4.7 75 2 (1) 27 VBS 10 AGND UCVBS 1.23 V (p-p)(2)
AGND
XTALI
DAC2
75 2 (1) 24 C 10 AGND
UVBS 1.00 V (p-p)(2)
DAC3
digital inputs and outputs
75
SAA7128H SAA7129H
DAC4
UC 0.89 V (p-p)(2)
2 (1) 23 RED
23
AGND
75 2 (1) 26 GREEN 23 AGND
UR 0.70 V (p-p)(2)
DAC5
SAA7128H; SAA7129H
75 2 (1) 29 BLUE 23 AGND
UG 0.70 V (p-p)(2)
DAC6
75 5, 18, 38 VSSD1 to VSSD3 (1) Typical value. (2) For 100100 colour bar. DGND 22, 32, 33 VSSA1 to VSSA3 AGND AGND
UB 0.70 V (p-p)(2)
Product specification
MHB583
Fig.24 Application circuit.
Philips Semiconductors
Product specification
Digital video encoder
9.1 Analog output voltages
SAA7128H; SAA7129H
The analog output voltages are dependent on the open-loop voltage of the operational amplifiers for full-scale conversion (typical value 1.35 V), the internal series resistor (typical value 2 ), the external series resistor and the external load impedance. The digital output signals in front of the DACs under nominal conditions occupy different conversion ranges, as indicated in Table 76 for a 100100 colour bar signal. Values for the external series resistors result in a 75 load. Table 76 Digital output signals conversion range CONVERSION RANGE (peak-to-peak) CVBS SYNC-TIP TO PEAK-CARRIER (digits) 1016 Y (VBS) SYNC-TIP TO WHITE (digits) 881 RGB (Y) BLACK TO WHITE AT GDY = GDC = -6 (digits) 712
2002 Oct 15
49
Philips Semiconductors
Product specification
Digital video encoder
10 PACKAGE OUTLINE
SAA7128H; SAA7129H
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
2002 Oct 15
50
Philips Semiconductors
Product specification
Digital video encoder
11 SOLDERING 11.1 Introduction to soldering surface mount packages
SAA7128H; SAA7129H
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 11.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 11.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 11.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 Oct 15
51
Philips Semiconductors
Product specification
Digital video encoder
11.5
SAA7128H; SAA7129H
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
not suitable not suitable(3)
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 12 REVISION HISTORY REV 2 2002 DATE - CPCN Modification: * Chapter 9; value of capacitor in the application circuit changed to 1 nF 1 20000308 - Product specification (9397 750 06127) DESCRIPTION Product specification (9397 750 09727)
2002 Oct 15
52
Philips Semiconductors
Product specification
Digital video encoder
13 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
SAA7128H; SAA7129H
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 14 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 15 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 Oct 15
53
Philips Semiconductors
Product specification
Digital video encoder
16 PURCHASE OF PHILIPS I2C COMPONENTS
SAA7128H; SAA7129H
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2002 Oct 15
54
Philips Semiconductors
Product specification
Digital video encoder
NOTES
SAA7128H; SAA7129H
2002 Oct 15
55
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753505/02/pp56
Date of release: 2002
Oct 15
Document order number:
9397 750 09727

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